An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 100. Each cell 100 contains a storage capacitor 140 and an access field effect transistor or transfer device 120. For each cell, one side of the storage capacitor 140 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor 140 is connected to the drain of the transfer device 120. The gate of the transfer device 120 is connected to a signal known in the art as a word line 180. The source of the transfer device 120 is connected to a signal known in the art as a bit line 160 (also known in the art as a digit line). With the memory cell 100 components connected in this manner, it is apparent that the word line 180 controls access to the storage capacitor 140 by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the bit line 160 to be written to or read from the storage capacitor 140. Thus, each cell 100 contains one bit of data (i.e., a logic “0” or logic “1”).
In FIG. 2 a DRAM circuit 240 is illustrated. The DRAM 240 contains a memory array 242, row and column decoders 244, 248 and a sense amplifier circuit 246. The memory array 242 consists of a plurality of memory cells 200 (constructed as illustrated in FIG. 1) whose word lines 280 and bit lines 260 are commonly arranged into rows and columns, respectively. The bit lines 260 of the memory array 242 are connected to the sense amplifier circuit 246, while its word lines 280 are connected to the row decoder 244. Address and control signals are input on address/control lines 261 into the DRAM 240 and connected to the column decoder 248, sense amplifier circuit 246 and row decoder 244 and are used to gain read and write access, among other things, to the memory array 242.
The column decoder 248 is connected to the sense amplifier circuit 246 via control and column select signals on column select lines 262. The sense amplifier circuit 246 receives input data destined for the memory array 242 and outputs data read from the memory array 242 over input/output (I/O) data lines 263. Data is read from the cells of the memory array 242 by activating a word line 280 (via the row decoder 244), which couples all of the memory cells corresponding to that word line to respective bit lines 260, which define the columns of the array. One or more bit lines 260 are also activated. When a particular word line 280 and bit lines 260 are activated, the sense amplifier circuit 246 connected to a bit line column detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line 260 by measuring the potential difference between the activated bit line 260 and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
The memory cells of dynamic random access memories (DRAMs) are comprised of two main components, a field-effect transistor (FET) and a capacitor which functions as a storage element. The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) cells which provides a substantial increase in component density. As component density has increased, cell capacitance has had to be decreased because of the need to maintain isolation between adjacent devices in the memory array. However, reduction in memory cell capacitance reduces the electrical signal output from the memory cells, making detection of the memory cell output signal more difficult. Thus, as the density of DRAM devices increases, it becomes more and more difficult to obtain reasonable storage capacity.
As DRAM devices are projected as operating in the gigabit range, the ability to form such a large number of storage capacitors requires smaller areas. However, this conflicts with the requirement for larger capacitance because capacitance is proportional to area. Moreover, the trend for reduction in power supply voltages results in stored charge reduction and leads to degradation of immunity to alpha particle induced soft errors, both of which require that the storage capacitance be even larger.
By using embedded memory rather than external memory, designers can maximize memory throughput to achieve higher system performance, introduce innovative architectures with customized memory sizes, and reduce power consumption in their systems. (See generallly, H. Takato et al., “Process Integration Trends for Embedded DRAM,” Proceedings of UlSI Process Integration, Electrochemical Society Proceedings, 99-18, 107-19 (1999); M. Mukai et al., “Proposal of a Logic Compatible Merged-Type Gain Cell for High Density Embedded.,” IEEE Trans. on Electron Devices, 46-6, 1201-1206 (1999)). Designers will also benefit from less expensive packaging, by removing the extra pins that drive external memory and by eliminating board space otherwise required by external memory chips. Both of these benefits can lower production costs. In addition, using embedded memory ensures users of a guaranteed supply of this type of memory, without the volatility of the external memory market.
One approach to embedded memory technology is based on the one transistor DRAM cell structure that utilizes the trench process employed in IBM's and Toshiba's DRAMs. (See generally, W. P. Noble et al., “The evolution of IBM CMOS DRAM Technology,” IBM J. Research and Development, 39-1/2, 167-188 (1995)). With trench technology, logic performance is not compromised. Trench technology provides a planar surface topology that enhances interconnect reliability while providing a DRAM storage capacitor with a large and conventional storage capacitance. However, additional masking levels are required in the logic technology to fabricate the trench capacitors.
Another approach to embedded memory is based on a three transistor DRAM cell structure, shown in FIG. 3. The three transistor DRAM cell structure was developed prior to the use of the trench capacitors or stacked capacitors now used in DRAMs. (See generally, J. Rabaey, Digital Integrated Circuits, Prentice Hall, 585-587 (1996)). A much smaller storage capacitor was utilized and compensated for by the gain of one of the transistors, in other words the first DRAMs developed used gain cells. These type of DRAM cells require only a minor modification of the conventional logic technology processes but occupy a large area due to the use of three transistors.
The inventors have previously disclosed a DRAM gain cell using two transistors. (See generally, L. Forbes, “Merged Transistor Structure for Gain Memory Cell,” U.S. Pat. No. 5,732,014, issued 24 Mar. 1998, continuation granted as U.S. Pat. No. 5,897,351, issued 27 Apr. 1999). A number of other gain cells have also been disclosed. (See generally, Sunouchi et al., “A self-Amplifying (SEA) Cell for Future High Density DRAMs,” Ext. Abstracts of IEEE Int. Electron Device Meeting, pp. 465-468 (1991); M. Terauchi et al., “A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMS,” VLSI Tech. Symposium, pp. 21-22 (1993); S. Shukuri et al., “Super-Low-Voltage Operation of a Semi-Static Complementary Gain RAM Memory Cell,” VLSI Tech. Symposium pp. 23-24 (1993); S. Shukuri et al., “Super-low-voltage operation of a semi-static complementary gain DRAM memory cell,” Ext. Abs. of IEEE Int. Electron Device Meeting, pp. 1006-1009 (1992); S. Shukuri et al., “A Semi-Static Complementary Gain Cell Technology for Sub-1 V Supply DRAM's,” IEEE Trans. on Electron Devices, Vol. 41, pp. 926-931 (1994); H. Wann and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate,” Ext. Abs. IEEE Int. Electron Devices Meeting, pp. 635-638; W. Kim et al., “An Experimental High-Density DRAM Cell with a Built-in Gain Stage,” IEEE J. of Solid-State Circuits, Vol. 29, pp. 978-981 (1994); W. H. Krautschneider et al., “Planar Gain Cell for Low Voltage Operation and Gigabit Memories,” Proc. VLSI Technology Symposium, pp. 139-140 (1995); D. M. Kenney, “Charge Amplifying trench Memory Cell,” U.S. Pat. No. 4,970,689, 13 Nov. 1990; M. Itoh, “Semiconductor memory element and method of fabricating the same,” U.S. Pat. No. 5,220,530, 15 Jun. 1993; W. H. Krautschneider et al., “Process for the Manufacture of a high density Cell Array of Gain Memory Cells,” U.S. Pat. No. 5,308,783, 3 May 1994; C. Hu et al., “Capacitorless DRAM device on Silicon on Insulator Substrate,” U.S. Pat. No. 5,448,513, 5 Sept. 1995; S. K. Banerjee, “Method of making a Trench DRAM cell with Dynamic Gain,” U.S. Pat. No. 5,066,607, 19 Nov. 1991; S. K. Banerjee, “Trench DRAM cell with Dynamic Gain,” U.S. Pat. No. 4,999,811, 12 Mar. 1991; Lim et al., “Two transistor DRAM cell,” U.S. Pat. No. 5,122,986, 16 Jun. 1992).
Recently a one transistor gain cell has been reported as shown in FIG. 4. (See generally, T. Ohsawa et al., “Memory design using one transistor gain cell on SOI,” IEEE Int. Solid State Circuits Conference, San Francisco, 2002, pp. 152-153). FIG. 4 illustrates a portion of a DRAM memory circuit containing two neighboring gain cells, 401 and 403. Each gain cell, 401 and 403, is separated from a substrate 405 by a buried oxide layer 407. The gain cells, 401 and 403, are formed on the buried oxide 407 and thus have a floating body, 409-1 and 409-2 respectively, separating a source region 411 (shared for the two cells) and a drain region 413-1 and 413-2. A bit/data line 415 is coupled to the drain regions 413-1 and 413-2 via bit contacts, 417-1 and 417-2. A ground source 419 is coupled to the source region 411. Wordlines or gates, 421-1 and 421-2, oppose the floating body regions 409-1 and 409-2 and are separated therefrom by a gate oxide, 423-1 and 423-2.
In the gain cell shown in FIG. 4 a floating body, 409-1 and 409-2, back gate bias is used to modulate the threshold voltage and consequently the conductivity of the NMOS transistor in each gain cell. The potential of the back gate body, 409-1 and 409-2, is made more positive by avalanche breakdown in the drain regions, 413-1 and 413-2, and collection of the holes generated by the body, 409-1 and 409-2. A more positive potential or forward bias applied to the body, 409-1 and 409-2, decreases the threshold voltage and makes the transistor more conductive when addressed. Charge storage is accomplished by this additional charge stored on the floating body, 409-1 and 409-2. Reset is accomplished by forward biasing the drain-body n-p junction diode to remove charge from the body.
Still, there is a need in the art for improved DRAM cell structures which can be based entirely on conventional CMOS logic technology, without additional masking and process steps, and which have a minimal cell area.